////////////////////////////////////////////////////
// File Name: crc32_v1_tb.v
// Author: zeping fan
// mail:   zpfan007@163.com
// Created Time: 2023年06月01日 星期四 19时36分47秒
/////////////////////////////////////////////////////


module crc32_v1_tb();

//parameter   NUM = 72;
parameter   NUM = 68;
    reg         clk;
    reg         rstn;
    reg [7:0]   din;
    reg         vld;
    reg         init;
    reg         calc;
    reg [8*NUM-1:0] mem  ;

    wire [7:0]  crc;
    wire [31:0] crc_reg;


    always #5 clk = ~clk;



    initial begin 
        //mem[NUM*8-1:0] = 'h0f1f2f3f4f5f0e1e2e3e4e5e8000_dcfe_1032547698badcfe_1032547698badcfe_1032547698badcfe_1032547698badcfe_1032547698badcfe_1032547698badcfe_10325476_a81706db;   //72B
        mem[NUM*8-1:0] = 'h0f1f2f3f4f5f0e1e2e3e4e5e8000_dcfe_1032547698badcfe_1032547698badcfe_1032547698badcfe_1032547698badcfe_1032547698badcfe_1032547698badcfe_10325476;            //68B
        //mem[NUM*8-1:0] = 'hf0f1f2f3f4f5e0e1e2e3e4e50800_cdef_0123456789abcdef_0123456789abcdef_0123456789abcdef_0123456789abcdef_0123456789abcdef_0123456789abcdef_01234567;              //68B
        //mem[NUM*8-1:0] = 'hf0f1f2f3f4f5e0e1e2e3e4e50800_cdef_0123456789abcdef_0123456789abcdef_0123456789abcdef_0123456789abcdef_0123456789abcdef_0123456789abcdef_01234567_38013a25;     //72B
    end

    initial begin
        $fsdbDumpfile("crc32.fsdb");
        $fsdbDumpvars(0,crc32_v1_tb);
        clk = 0;
        rstn = 0;
        din = 8'b0;
        vld = 0;
        calc = 0;
        init = 0;
        repeat(2) @(posedge clk);#0;
        rstn = 1;
        @(posedge clk);#0;
        initilize;
        datain;


        #100;
        $finish;

    end

task initilize;
    begin
        init = 1;
        @(posedge clk);#0;
        init = 0;
        repeat(2)@(posedge clk);#0;
    end
endtask




task datain;
    begin 
        calc = 1'b1;
        @(posedge clk);#0;
        for(integer i=NUM; i>0; i=i-1)begin
            vld = 1'b1;
            din = mem[8*i-1-:8];
            @(posedge clk);#0;
        end
/*
        din = 8'h96;
        @(posedge clk);#0;
        din = 8'h25;
        @(posedge clk);#0;
        din = 8'hb7;
        @(posedge clk);#0;
        din = 8'h5a;
        @(posedge clk);#0;
*/
        vld = 1'b0;
        din = 8'b0;
        repeat(4)@(posedge clk);#0
        calc = 1'b0;
        @(posedge clk);#0;
    end
endtask        




crc32_v1 u1_crc32(
    .clk(clk),
    .rstn(rstn),
    .d(din),
    .vld(vld),
    .init(init),
    .calc(calc),
    .crc_reg(crc_reg),
    .crc(crc)
);




endmodule
